VHDL
Tutorial: Learn by Example
--
by Weijun Zhang, July 2001
*** NEW (2010): See the new book VHDL for Digital Design, F. Vahid and R. Lysecky, J. Wiley and Sons, 2007. Concise (180 pages), numerous examples, low-cost. Also see www.ddvahid.com.***
If we hear, we forget;
if we see, we remember; if we do, we understand.
-- Proverb
ESD
book | Dalton Project
| VHDL
Reference | Synopsys
Tutorial | ActiveHDL
Tutorial | Xilinx
Tutorial
Table of Contents
Foreword
Foreword (by Frank Vahid)
HDL (Hardware Description Language) based design has established itself
as the modern approach to design of digital systems, with VHDL (VHSIC Hardware
Description Language) and Verilog HDL being the two dominant HDLs.
Numerous universities thus introduce their students to VHDL (or Verilog).
The problem is that VHDL is complex due to its generality. Introducing
students to the language first, and then showing them how to design
digital systems with the language, tends to confuse students. The
language issues tend to distract them from the understanding of
digital components. And the synthesis subset issues of the language
add to the confusion.
We developed the following tutorial based on the philosophy that
the beginning student need not understand the details of VHDL -- instead,
they should be able to modify examples to build the desired basic
circuits. Thus, they learn the importance of HDL-based digital design,
without having to learn the complexities of HDLs. Those complexities
can be reserved for a second, more advanced course.
The examples are mostly from the textbook Embedded
System Design by Frank Vahid and Tony Givargis. They
start from basic gates and work their way up to a simple microprocessor.
Most of the examples have been simulated by
Aldec
ActiveHDL Simulator and Synopsys
Design Analyzer, as well as synthesized with Synopsys Design Compiler .
Several sequential design examples have
been successfully tested on
Xilinx
Foundation Software and FPGA/CPLD board.
Basic Logic Gates
(ESD Chapter 2: Figure 2.3)
Every VHDL design
description consists of at least one entity / architecture pair,
or one entity with multiple architectures. The entity section of the HDL
design is used to declare the I/O ports of the circuit, while the
description code resides within architecture portion. Standardized design
libraries are typically used and are included prior to the entity declaration.
This is accomplished by including the code "library ieee;" and "use ieee.std_logic_1164.all;".
Combinational Logic Design
(ESD Chapter 2: Figure 2.4)
We use port
map statement to achieve the structural model (components instantiations).
The following example shows how to write the program to incorporate multiple
components in the design of a more complex circuit. In order to simulate
the design, a simple test bench code must be written to apply a
sequence of inputs (Stimulators) to the circuit being tested (UUT).
The output of the test bench and UUT interaction can be observed in the
simulation waveform window.
Discussion I: Signal vs. Variable:
Siganls are used
to connect the design components and must carry the information between
current statements of the design. On the other hand, variables are
used within process to compute certain values. The following example shows
their difference:
Typical Combinational Components
(ESD Chapter 2: Figure 2.5)
The following
behavior style codes demonstrate the concurrent and sequential capabilities
of VHDL. The
concurrent statements are written within the body of
an architecture. They include concurrent signal assignment, concurrent
process and
component instantiations (port map statement). Sequential
statements are written within a process statement, function
or
procedure. Sequential statement include case statement,
if-then-else
statement and loop statement.
Latch & Flip-Flops
(ESD Chapter 2.3)
Besides from the
circuit input and output signals, there are normally two other important
signals,
reset and clock, in the sequential circuit. The
reset signal is either active-high or active-low status and
the circuit status transition can occur at either clock rising-edge
or falling-edge. Flip-Flop is a basic component of the sequential
circuits.
Typical Sequential Components
(ESD Chapter 2: Figure 2.6)
Typical sequential
components consist of registers, shifters and counters. The concept of
generics
is often used to parameterize these components. Parameterized components
make it possible to construct standardized libraries of shared models.
In the behavioral description, the output transitions are generally set
at the clock rising-edge. This is accomplished with the combination of
the VHDL
conditional statements (clock'event and clock='1'). During
the testbench running, the expected output of the circuit is compared with
the results of simulation to verify the circuit design.
Sequential Logic Design
(ESD Chapter 2: Figure 2.7)
The most important
description model presented here may be the Finite State Machine (FSM).
A general model of a FSM consists of both the combinational Logic and sequential
components such as state registers, which record the states of circuit
and are updated synchronously on the rising edge of the clock signal. The
output function computes the various outputs according to different states.
Another type of sequential model is the memory module, which usually takes
a long time to be synthesized due to the number of design cells.
Memories (ESD Chapter 5)
Discussion II: Behavior vs. RTL Synthesis
(Y
Chart)
RTL stands for Register-Transfer
Level. It is an essential part of top-down digital design process.
Logic
synthesis offers an automated route from an RTL design to a Gate-Level
design. In RTL design a circuit is described as a set of registers and
a set of transfer functions describing the flow of data between the registers,
(ie. FSM + Datapath). As an important part of a complex design,
this division is the main objective of the hardware designer using synthesis.
The Synopsys Synthesis Example illustrates that the RTL synthesis is more
efficient than the behavior synthesis, although the simulation of previous
one requires a few clock cycles.